The present invention relates to apparatus for performing digital or binary division. In particular the invention is a special purpose pipelined divider for use when the dividend is smaller than the divisor. A particularly useful application is in the division of quadrature related signals for determining the tangent defined by their ratio or more specifically the arctangent.
Binary division is typically a time-consuming operation with currently available devices precluding real time division at high sample rates, or requires a relatively large number of devices to perform high speed division. One method of high speed division of the latter category is performed by determining the reciprocals of the divisor and multiplying the dividend with the reciprocals. The reciprocals may be obtained from a look-up memory such as a ROM. But as is well known by those skilled in the art of binary digital signal processing, high speed binary multipliers are both very complex and consume significant power.
Low speed dividers on the other hand are considerably less complex and operate on the principle of successive subtractions. Straight forward successive subtraction is performed as follows. The dividend is loaded into a register having parallel output terminals. The output terminals are coupled to the minuend input port of a binary subtraction circuit. The divisor is coupled to the subtrahend input port of the subtraction circuit. The difference produced is subsequently loaded into the register and the divisor subtracted therefrom. This process is iterated until a zero or negative difference is produced. Each of the respective subtractions increment a counter circuit. The value in the counter after the first zero or negative difference is produced corresponds to the desired quotient. It is readily realized that this iterative method requires a significant number of process operations rendering the procedure relatively slow.
This latter procedure can be increased in speed if the individual subtractions for successive quotients are performed in parallel so that successive final quotients are produced at the sample rate. That is, the calculations are pipelined. The procedure is further simplified for quotients of fixed accuracy if the divisor is always smaller than the dividend so that a minimum number of processing steps will produce the desired accuracy.